1. Field of the Invention
The present invention relates to a radiographic image detector and a method for controlling the radiographic image detector.
2. Description of the Related Art
In the medical field, radiography systems utilizing radioactive rays, such as x-rays, for imaging are widely known. An x-ray radiography system, an example of radiography systems, includes an x-ray projector for projecting x-rays toward a subject or patient and an x-ray imaging apparatus for acquiring a radiograph or x-ray image of the subject from the x-rays that have penetrated the subject. The x-ray projector includes an x-ray source, a source controller unit for controlling the x-ray source, and an activation switch for inputting a command for actuating the x-ray source to the source controller. The x-ray imaging apparatus includes an x-ray image detector for detecting an x-ray image or x-ray images from incident x-rays, and a console for controlling operation of the x-ray image detector, storing and displaying the x-ray images.
X-ray image detectors using a flat panel detector (FPD) as an imaging device have recently been widely spread. The FPD has an imaging area in which an array of pixels are provided for accumulating signal charges corresponding to x-rays that are incident on the respective pixels. Each pixel includes a photoelectric conversion element for generating and accumulating the charges and a switching element, such as a thin film transistor (TFT). In the FPD, the accumulated signal charges are read out from the photoelectric conversion elements of the pixels line by line of the pixel array when the switching elements are turned on, and are fed through signal lines, which are provided one for each column of the pixel array, to a signal processing circuit. In the signal processing circuit, the signal charges are converted to a voltage signal, electrically detecting an x-ray image of the subject.
The signal processing circuit is provided with integrating amplifiers, correlated double sampling (CDS) circuits, A/D converters and etc. The integration amplifiers are individually provided on each signal line that is connected to respective pixels of one column, so that each integration amplifier integrates the signal charges from the signal line to convert the signal charges to an analog voltage signal. The CDS circuits are also provided for the individual signal lines, being connected to respective output terminals of the integration amplifiers. The CDS circuit includes a sample-and-hold circuit, which renders the analog voltage signal from the integration amplifier with correlated double sampling for noise reduction, and holds the analog voltage signal for a predetermined time in the sample-and-hold circuit. The A/D converter converts the analog voltage signal as held in the sample-and-hold circuit to a digital voltage signal and outputs the same to a frame memory which is capable of recording the digital voltage signal in a unit corresponding to a frame of x-ray image. The signal processing circuit is further provided with amplifiers for amplifying the analog voltage signals, and a multiplexer which sequentially selects the sample-and-hold circuits of the CDS circuits of the respective pixel columns to feed the analog voltage signal selectively from one sample-and-hold circuit to the A/D converter.
U.S. Pat. No. 7,122,802 (corresponding to Japanese Patent Laid-Open Publication No. 2004-000564) describes a signal processing circuit which is provided with integration amplifiers (reading portion circuits), an A/D converter (converting portion circuit), and first and second buffer memories (line buffers) located in between the A/D converter and a memory (collecting subsystem). The first and second buffer memories are line memories, each of which is capable of recording the digital voltage signal from a line of pixels of the pixel array, which corresponds to a line of x-ray image. An image reading operation for reading a frame of x-ray image is executed by the signal processing circuit in the manner as shown in FIG. 16. The signal processing circuit executes so-called pipeline processing, wherein an image signal P(N), which is an analog voltage signal obtained by converting signal charges p(N) of a line of pixels through integration amplifiers in one image reading cycle (Nth cycle), is sampled and held in CDS circuits immediately before the next or (N+1)th cycle; the sampled and held image signal P(N) is converted to a digital image signal Pd(N) through the A/D converter and the digital image signal Pd(N) is temporarily stored in the first buffer memory in the (N+1)th cycle (see “AD Data” of FIG. 16); and the image signal Pd(N) is output from the first buffer memory (see “Data Out” of FIG. 16) in the cycle after the next, the (N+2)th cycle. Accordingly, in one cycle, a signal inputting operation, i.e. analog-to-digital conversion of an image signal through the A/D converter and temporary storage of the image signal in one buffer memory, is carried out in parallel or concurrently with a signal outputting operation, i.e. reading a digital image signal Pd(N−1) from the other buffer memory, the signal Pd(N−1) having been temporarily stored in the preceding cycle.
The buffer memory cannot store the voltage signal for one line unless the previously stored voltage signal for one line is output from the same buffer memory. Accordingly, if there is merely one buffer memory in the signal processing circuit, it is impossible to make the pipeline processing or parallel input and output of the voltage signals. Therefore, one cycle from the start of reading the analog voltage signal for one line till the end of writing the corresponding digital voltage signal in the memory inevitably involves the time for inputting the voltage signal in the buffer memory plus the time for outputting the same signal from the buffer memory.
In contrast to this, the pipeline-type signal processing circuit described in the prior art, as having the dual buffer memories, can make outputting operation of the voltage signal, which has been written in one buffer memory in the preceding cycle, simultaneously with inputting operation of the voltage signal, which has been sampled and held in the CDS circuits in the current cycle, into the other buffer memory. In other words, the signal inputting operation for one line and the signal outputting operation for the preceding line are simultaneously executed in one cycle. Therefore, the pipeline processing will cut the time taken for reading out a frame of image nearly in half as compared to the case using a single buffer memory. However, because the voltage signal for one line is read out from the buffer memory in the cycle next to the cycle in which the same voltage signal was written in the same buffer memory, the time lag from the sampling of analog image signal “P”, obtained by integrating the signal charges “p” for one line, till the output of corresponding digital voltage signal “Pd” from the signal processing circuit gets approximately equal to one cycle period “T”.
In FIG. 16, “Sync” represents a synchronizing signal which determines the period T of one cycle in which the signal processing circuit executes sampling and holding of the analog image signal P, digital conversion to the digital image signal Pd, temporary storage of the digital image signal Pd, and outputting of the digital image signal; “Internal Reset” represents a signal for executing at least one of those resetting operations for resetting charges in the integration amplifiers, resetting the sampling and holding in the CDS circuits, and selective resetting of the CDS circuits from selected condition to unselected condition; and “Analog Clock” represents a signal for timing the control of operations of the integration amplifiers and the CDS circuits, which constitute an analog signal processing circuit (analog front end). Specifically, the Analog Clock signal determines the timing of charge integration in the integration amplifiers, the timing of outputting the voltage signals to the CDS circuit, the timing of sampling and holding, and etc. “ADC Clock” and “Buffer Data Clock” represent control signals for the A/D converter and the buffer memories, respectively.
The chart “Active Buffer” indicates which buffer memory is used for writing the image signal Pd in the current cycle. Namely, the first and second buffer memories alternately serve as the active buffer, switched over with each cycle. For example, the image signal Pd(N) of one line is temporarily stored in the first buffer memory, and the image signal Pd(N+1) of the next line in the second buffer memory.
In the FPD type image detector, because the pixels accumulate unnecessary charges that result from dark currents or residual charges from the previous imaging may remain in the pixels, the FPD periodically carries out charge-resetting operation for clearing unnecessary charges off the pixels before starting charge accumulating operation, in order to reduce the influence of dark charge noises on x-ray images to the minimum. Accordingly, it is generally necessary for the radiography system using the FPD to synchronize the timing of x-ray radiation with the end of charge-resetting operation and the start of charge accumulating operation. For this purpose, in one radiography system, the source controller unit and the x-ray image detector are provided with interfaces (I/F) to establish mutual communication therebetween. The source controller unit sends a synchronizing signal to the electronic cassette at the time of starting x-ray radiation, so that the synchronizing signal triggers the x-ray image detector to proceed to the accumulating operation.
In another radiography system, the x-ray image detector and the source controller are not connected nor exchange any synchronizing signal with each other. Instead, a dose sensor is provided to measure the amount of radiated x-rays. The measured x-ray amount is compared with a predetermined threshold level so as to determine the start of radiation from the x-ray source when the x-ray amount goes over the threshold level. Upon the start of radiation being detected, the x-ray image detector drives the FPD to start charge accumulating operation. Likewise, the amount of x-rays measured by the dose sensor may be compared with another threshold level for determining the end of radiation from the x-ray source and driving the FPD to proceed from charge accumulating operation to reading operation.
Some radiography systems make an automatic exposure control (AEC), whereby the amount of x-rays dosed onto the subject is measured by a dose sensor during the imaging (exposure to x-rays) in order to stop x-ray radiation from the x-ray source when the integrated amount of x-rays measured by the dose sensor gets to a predetermined threshold level. Simultaneously, the x-ray image detector is controlled to proceed from charge accumulating operation to reading operation. The amount of x-rays radiated from the x-ray source is determined as a product of tube current and radiation time (mAs), because the tube current determines the amount per unit time of x-rays from the x-ray source. Although there are recommendable values for image acquisition settings, including the radiation time and the tube current, predetermined according to the target site of the subject, such as chest or head, the sex and age of the subject and the like, x-ray permeability also varies from individual to individual, e.g. depending upon the body constitution of the subject. Therefore, the AEC processing is conducted for acquiring more adequate image quality.
Conventionally, an ion chamber or the like has been used as a dose sensor. However, many techniques of modifying pixels of the FPD so as to serve the modified pixels as detective pixels for detecting the amount of radiation or dose have recent been suggested. For example, U.S. Patent Application Publication No. 2011/0180717 (corresponding to Japanese Patent Laid-Open Publication No. 2011-174908) describes connecting some pixels to a detective line for detecting radiation, not to the signal lines, directly without any switching element therebetween, such that charges generated in these pixels flow through the detective line regardless of ON-OFF operation of switching elements of ordinary pixels. The detective line is connected to a signal processing circuit, so that the signal processing circuit samples a voltage signal corresponding to the charges generated from the detective pixels, hereinafter referred to as the dose detection signal, at predetermined intervals. The sampled voltage signal is input to a controller, so that the controller makes an AEC (automatic exposure control) or detects a start or an end of x-ray radiation from the x-ray source on the basis of the dose detection signal.
According to the discloser in U.S. Patent Application Publication No. 2011/0180717 (corresponding to Japanese Patent Laid-Open Publication No. 2011-174908), the detective pixels are connected to the specific detective line for dose detection, and the detective line is connected to the specific signal processing circuit used especially for dose detecting operation. As an alternative, it has also been suggested that ordinary signal lines for ordinary pixels and a signal processing circuit for image signals may also serve to acquire the dose detection signal from the detective pixels. More than one detective pixel may be connected to one signal line. In the dose detecting operation, signal charges from the detective pixels are read out all at once through respective signal lines at each sampling operation.
In a radiography system in which the dose detection signal is acquired through signal lines for ordinary pixels and a signal processing circuit for image signals, if the signal processing circuit is configured to make the above-described pipeline processing, a problem could occur in relation to the AEC processing. That is, there would be a certain delay in deciding the time to stop the x-ray radiation or in detecting the start or the end of x-ray radiation. As a result, the subject could be overexposed, or the delay in operation of the FPD could result an artifact in the consequent x-ray image, degrading the image quality. The reason for such problem is because the pipeline-type signal processing circuit involves the time lag of approximately one cycle period from the integration of the signal charges till the output of the corresponding digital voltage signal (or the dose detection signal). If, for example, the x-ray radiation starts actually at the same time as the integration amplifiers start integration, the start of radiation will be determined on the basis of the dose detection signal with such a delay time that is almost triple the cycle period.
Specifically, when the pipeline-type signal processing circuit is used for the dose detecting operation, if the processing circuit would operate in constant cycles in the same manner as for the image reading operation as shown in FIG. 16, timing charts of the dose detecting operation would be as shown in FIG. 17. The timing charts of FIG. 17 are substantially equal to those of FIG. 16, but the image signals (signal charges “p” of the pixels, the analog image signal “P” and the digital image signal “Pd”) are replaced with dose detection signals (signal charges “s” of the detective pixels, an analog dose detection signal “S” and a digital dose detection signal “Sd”), and one cycle period is designated by Ts.
In the image reading operation, the image signal is read line-sequentially, i.e., one line in each cycle T, so that the time taken for reading out a frame of image (all pixels) approximately equals T multiplied by the total number of lines. On the other hand, the dose detecting operation is configured to read the charges from the detective pixels at once through the respective signal lines, so that the charges of all detective pixels are sampled as a dose detection signal in each cycle Ts. For detecting the start of radiation, a dose detection signal obtained through the current or Nth time of sampling is compared with a dose detection signal obtained through the preceding or (N−1)th time of sampling, to determine whether the signal level increases or not.
As described above, the conventional pipeline-type signal processing circuit involves the time lag of approximately one cycle period Ts from the integration of the signal charges till the output of the corresponding digital voltage signal. Therefore, if, for example, the x-ray radiation starts actually at the start of the Nth sampling (integration of charges s(N) of the detective pixels through the integrating amplifiers), as shown in FIG. 17, the digital dose detection signal Sd(N) obtained through the Nth sampling will be output from the buffer memory with a delay time of almost triple the cycle period (3Ts). This results in a corresponding delay in determining the start of radiation.
Beside the above problem, since the response of the x-ray source is low and hence the dose amount shows a small change per unit time in the initial stage of radiation, the cycle period Ts (50 to 500 μsec.) for sampling the dose detection signal is preferably set longer than the cycle period T for reading the image signal P, in order to ensure a sufficient S/N ratio. With the elongated cycle period Ts, the delay of almost triple the cycle period, due to the pipeline processing, cannot be ignored as a margin of error in the dose detecting operation. Particularly, when each radiation time is set as short as several micro seconds for the sake of total dose reduction, i.e. minimum exposure to x-rays, the delay of detection causes an unignorable problem.
The above prior arts do not disclose any solution for the above problem in obtaining the dose detection signal from the dose sensor through the pipeline-type signal processing circuit.